Communication developments in the last decade have demonstrated what seems to be a migration from parallel data input/output (I/O) interface implementations to a preference for serial data I/O interfaces. Some of the motivations for preferring serial I/O over parallel I/O include reduced system costs through reduction in pin count, simplified system designs, and scalability to meet the ever increasing bandwidth requirements of today's communication needs. Serial I/O solutions will most probably be deployed in nearly every electronic product imaginable, including IC-to-IC interfacing, backplane connectivity, and box-to-box communications.
Although the need for increased communication bandwidth continues to drive future designs, support for the lower bandwidth legacy systems still remains. As such, the future designs are required to provide a wide range of scalability, whereby data rate, slew rate, and many other physical (PHY) layer attributes are adaptable. For example, a particular transmitter/receiver (TX/RX) pair may be configured for use as both a high-definition serial digital interface (HD-SDI) and a standard-definition serial digital interface (SD-SDI). Both standards have similar specifications, but differ from each other at the PHY layer with respect to, for example, bit rate and edge rate. In order to provide a cost effective solution for both interfaces, the same transmitter/receiver pair may be required to adapt to both specifications by changing its mode of operation.
The bit rate, for example, of the PHY layer may determine the particular mode of operation that is implemented by each transceiver. A lower bit rate, for example, of the PHY layer may dictate that an over-sampling of the input data stream may be employed, whereby the recovered clock signal is digitally reconstructed from a local clock reference. Conversely, a faster bit rate of the PHY layer may preclude the use of over-sampling, such that a clock and data recovery (CDR) circuit is used instead to generate the recovered clock signal from data transitions that are detected in the input data stream.
The recovered clock signal, however, may exhibit certain detrimental characteristics depending upon the mode in which it is generated. For example, the over-sampled version of the recovered clock signal may contain an excessive amount of spurious frequency content, which may preclude its use with conventional clean-up phase locked loops (PLLs), thus requiring a more robust phase/frequency detector. Alternatively, the CDR recovered clock signal may exhibit reduced spurious frequency content, thus allowing the use of a less robust phase/frequency detector. Efforts continue, therefore, to provide flexible designs that offer efficient functionality over a broad range of applications.